1. Field of the Invention
The present invention relates to a semiconductor testing apparatus and semiconductor testing method for testing a semiconductor device for, for example, a television, a video tape recorder (VTR), a digital versatile disk (DVD) and audio application.
Further, the present invention relates to an apparatus and method for optimizing a wait time involved until an output signal of a semiconductor device becomes stable in the measurement of the electrical characteristics of the semiconductor device, such as the voltage, current, waveform, timing, phase, etc., of the output signal. In particular, the present invention is used for debugging a semiconductor device.
2. Description of the Related Art
Generally, resin-molded semiconductor device packages and wafer-state semiconductor devices before die-sorting are tested for their electrical characteristics and, based on the results, an OK/NG (OK/No Go) decision is made. When a semiconductor device is tested by the semiconductor testing apparatus for electrical characteristics, the testing apparatus optimizes a wait time involved until an output signal becomes stable. Here, a stable output signal means a state in which data values measured a plurality of times are similar to within a few percent. Therefore, an unstable output signal means a state in which data values measured a plurality of times are not similar to within a few percent. Further, a plurality of times means that the same measurement of for example, voltage is repeated, for example, 10 or 20 times.
Conventionally, optimization of the wait time is repeatedly made by human operation, by selecting the testing items for the optimization of the wait time and confirming data values following a change in the wait time.
In recent times, however, the number of items tested of the semiconductor device have enormously increased, thus much more time is needed in optimization operations on resultant wait times. These items include DC and AC measurement, function tests, etc. Various kinds of DC measurement are performed, and for each one the input signal value is varied, thus inevitably increasing the number of items involved.
As is set out above, the conventional method for optimizing the semiconductor testing time takes a lot of time.